Based on FPGA EP1K10QC208-3 chip to realize the design of 256-level grayscale LED dot matrix screen control system

256-level grayscale LED dot matrix screens are increasingly showing their broad application prospects in many fields. This article proposes a new control method, namely, bit-by-bit time-sharing control. With the emergence of large-scale programmable logic devices, high-speed and complex control completed by pure hardware becomes possible.

introduction

256-level grayscale LED dot matrix screens are increasingly showing their broad application prospects in many fields. This article proposes a new control method, namely, bit-by-bit time-sharing control. With the emergence of large-scale programmable logic devices, high-speed and complex control completed by pure hardware becomes possible.

The working principle of time-sharing lighting

The so-called bit-by-bit time-sharing lighting means that one bit of data is sequentially extracted from one byte of data, and the corresponding pixel is illuminated in 8 times. Each bit corresponds to a different duty cycle for each turn-on time and turn-off time. . If the lighting time increases from low to high, the combined lighting time will have 256 combinations. Define the on time plus the off time as a time unit, set as T. Table 1 lists the time allocation for each bit to turn on and off.

If the defined data bit “1” is valid (lit) and “0” is invalid (off), Table 2 lists the different lighting times when the data is from 00H to FFH. It can be seen from Table 2: Every time the data increases by 1, the lighting time increases by T/128. According to the principle that the lighting time and the brightness are basically linear, the lighting time from 0 to 255T/128 corresponds to 256 levels of brightness. Of course, this brightness is a cumulative effect over time. If the same data bit corresponding to all pixels of an LED dot matrix screen is lit once, it is called a field, then 8 fields of 8-bit data need to be displayed in total, which is called the “8 field principle”.

Theoretically speaking, 8 fields can Display 256 levels of gray. However, it can be seen from Table 2 that even when the data is FFH, it only lights up 255T/128 time in 8T time. The turn-off time can be close to 6T, and the lighting time is only about 25% of the total time. Therefore, although the 8-field principle can achieve 256-level grayscale Display, the brightness loss is too large. In order to improve the brightness, the “19-field principle” can be used, that is, the 8-bit data is displayed in 19 fields, in which the D7-bit data is continuously displayed for 8 fields, and the D6-bit data is continuously displayed for 4 fields, successively decreasing. Table 3 lists the turn-on and turn-off times of each individual.

From Table 3, the total lighting time of the data from 00H to FFH range can be derived, as shown in Table 4. In 19T, the maximum lighting time can reach nearly 16T, accounting for 84.21% of the total time, which is much greater than 25% of the “8-field principle”. Every time the data increases by 1, the lighting time increases by T/16, which is greater than T/128 of the “8-field principle”. Therefore, the contrast of the “19 field principle” is more obvious than that of the “8 field principle”, and the image has clear layers and strong expressiveness.

  Based on FPGA EP1K10QC208-3 chip to realize the design of 256-level grayscale LED dot matrix screen control system

Circuit design

256-level grayscale LED dot matrix screen usually has the function of remotely and synchronously displaying computer video signals in real time. The circuits involved include: digital video signal acquisition, digital signal format conversion and nonlinear correction, remote transmission and reception, grayscale Degree display control circuit, LED dot matrix display circuit, etc. This article focuses on the design of the “grayscale display control circuit”. The control objects are red and green dual-color LED dot matrix screens and 1/16 scan display circuits as examples. The internal circuit of FPGA is shown as in Fig. 1.

Because the controlled object is a 1/16 scan display circuit, only one data signal is needed for every 16 lines of the display screen. DRout1 and DGout1 are the red and green primary color output signals of the first 16 rows; DRout2 and DGout2 are the red and green primary color output signals of the second 16 rows. And so on.

The binary codes of Ha, Hb, Hc, and Hd define which of the 16 rows the current data output should be. The CP signal is a synchronous shift pulse for data serial output. The LE signal is a latched pulse after the output of a line of serial data is completed. Each time LE is effective, the binary code status of Ha, Hb, Hc, and Hd increases by 1. EA is a gray scale control signal, and its width is the lighting time of the LED in a time unit T. Of course, different data bits have different widths, which are specifically determined by Table 3. A time unit T is the transmission time of a line of serial data, that is, the period of the LE signal, and its size depends on the number of pixels of the screen width and the frequency of the CP signal.

DRin1~8 and DGin1~8 are red and green data input signals, corresponding to the first 16-row dot matrix area to the eighth 16-row dot matrix area respectively. Cpin is the synchronization pulse, one pulse corresponds to one bit of data, and 8 pulses correspond to the 8-bit data input of one pixel. The H signal is a line synchronization pulse. When one line of data input ends, the H signal is valid once. V is the frame synchronization pulse, one frame (16 lines) data input ends, the V signal is valid once. The above-mentioned signals are all signals provided by the previous system.

Two sets of high-speed static RAM are connected outside FPGA (not shown in the figure). DRA1~8 and DGA1~8 are the red and green data lines of group A RAM, and DRB1~8 and DGB1~8 are the red and green data lines of group B RAM. Data line; /WRA, /RDA are the read and write control signals of group A, /WRB, /RDB are read and write control signals of group B; AA0~16 are address lines of group A, and AB0~16 are group B Address line. The purpose of using two sets of RAM is to ensure that the read and write operations to the RAM can be carried out at the same time. When writing RAM (A), read RAM (B); when writing RAM (B), read RAM (A). The write/read switching of the two is controlled by the frame signal V. Each time V is valid, a switch is performed.

Cpin is the write pulse provided by the previous system, and also serves as the count pulse of the write address generating circuit. The count address range is A0~A16, a total of 128K bytes, of which A0~A2 are the gray-scale data addresses (decided to access the 8-bit data Who). A3~A12 are the pixel addresses in the X direction, and A13~A16 are the pixel addresses in the Y direction, that is, the row address. When the H signal comes, clear A0~A12, and add 1 to the A13~A16 address. When the V signal comes, A0~A12 and A13~A16 are all cleared. The above address is used as the write address of RAM.

CLK is the count pulse of the read address generating circuit (provided by the external circuit), the count address range is also A0~A16, a total of 128K bytes, where A0~A9 are the pixel addresses in the X direction, and A10~A13 are the pixel addresses in the Y direction, that is, row address. A14~A16 are gray-scale data addresses. The above addresses are used as the read addresses of the RAM. The change rule of these addresses should conform to the change rule of the “19 field principle” for the address requirements, that is: A0~A9 are cleared when they are full, and a row signal, namely, the LE signal, is generated. The LE signal is used as the counting pulse of A10~A13. After A10~A13 is full, it will be cleared to generate a field signal. The field signal is used as the counting pulse of A14~A16. However, A14~A16 is not a simple binary count, and its rules are shown in Table 5. In order to correctly read the data written to the RAM, the generated read address should be connected to the RAM according to the method shown in Table 6.

The function of the read and write control circuit is to provide read and write control signals to the two sets of RAM. The logical relationship is shown in Table 7. The function of the data input/output circuit is to switch the direction of data transmission, as shown in Table 8.

The function of the frame switching circuit is to generate the switching signal S required by the above-mentioned circuit. The method of realization is that every time the frame synchronization pulse V is effective, the logic state of S is reversed once. The frame switching circuit ensures that the two groups of RAM continue to read and write with the V signal.

The gray signal generating circuit generates the EA signal required by the controlled object, which changes with the status of the read addresses A14, A15, and A16. The logical relationship is shown in Table 9.

According to the principle of frame period Tp=20ms and one frame=19 fields, the following calculation results can be obtained: Field period Tv=Tp/19=1.05ms; Line period T=Tv/16=66ms; Output shift pulse period Tcp=T/ 1024=64ns; output shift pulse frequency fcp=1/Tcp=15.6MHz. CLK signal frequency fclk=fcp=15.6MHz; In actual application, the CLK clock signal frequency is selected as 16MHz.

In the MAX PLUSII10.0 environment, the design of the above circuit is completed using graphics and hardware description language.

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