Maximize the performance of your Sigma-Delta ADC driver

The design of an amplifier stage consists of two distinct stages that are interrelated, so the problem becomes difficult to model mathematically, especially due to the nonlinearities associated with the two stages. The first step is to choose an amplifier that will buffer the sensor output and drive the ADC input. The second step is to design a low-pass filter to reduce the input bandwidth, thereby minimizing out-of-band noise.

Author: Stuart Servis

Have you checked how many entries on the network are “ADC’s design buffer”? It’s hard to find what you’re looking for in over 4 million references. This may come as no surprise to most analog and mixed-signal data acquisition system design engineers, since designing an external front end for an unbuffered analog-to-digital converter (ADC) requires a lot of patience and advice. It is often seen as an art form, a treasure for eccentric masters who have mastered their craft over the years. For the uninitiated, it’s a frustrating trial and error. Most of the time, frustration becomes an annoying companion due to the number of interrelated norms that force many tradeoffs (and evaluations) until the best outcome is achieved.


The design of an amplifier stage consists of two distinct stages that are interrelated, so the problem becomes difficult to model mathematically, especially due to the nonlinearities associated with the two stages. The first step is to choose an amplifier that will buffer the sensor output and drive the ADC input. The second step is to design a low-pass filter to reduce the input bandwidth, thereby minimizing out-of-band noise.

An ideal amplifier provides just enough bandwidth to properly buffer the signal produced by a sensor or transducer without adding additional noise and provides zero power consumption, but an ideal amplifier is far from a true amplifier. In most cases, the amplifier specification will define the overall system performance, especially in terms of noise, distortion and power. To better understand the problem, the first step is to understand how discrete-time ADCs work.

A discrete-time ADC takes samples of a continuous-time analog signal, which is then converted to a digital code. When sampling a signal, depending on the type of analog converter, there are two different cases with the same inherent problem.

SAR ADCs integrate a sample-and-hold, also known as sample-and-hold, which is basically a switch and a capacitor that freezes the analog signal until the conversion is complete, as shown in Figure 1.

Maximize the performance of your Sigma-Delta ADC driver
Figure 1. Sample and hold circuit diagram.

A discrete-time sigma-delta ADC or oversampling converter implements a similar input stage, an input switch with some internal capacitance. In the case of a sigma-delta ADC, the sampling mechanism is slightly different, but a similar sampling input architecture occurs where switches and capacitors are used to hold a copy of the analog input signal.

In both cases, the switch is implemented in a CMOS process with a non-zero resistance value when closed, typically a few ohms. This series resistance, combined with the sampling capacitor, in the pF range means that the ADC input bandwidth is usually very large, and in many cases much larger than the ADC sampling frequency.

bandwidth issues

Input signal bandwidth is a converter problem. In sampling theory, we know that frequencies higher than the Nyquist frequency (half the ADC sampling frequency) should be removed, otherwise these frequencies will produce images or aliasing in the frequency band of interest. Noise usually has a spectrum where a large amount of power may be present in the frequency band above the Nyquist frequency of the ADC. Unless we deal with this noise, it will alias below the Nyquist frequency and increase the noise floor, as shown in Figure 2, effectively reducing the dynamic range of the system.

Maximize the performance of your Sigma-Delta ADC driver
Figure 2. Nyquist fold image.

ADC input signal bandwidth and extended buffer output bandwidth are the first issues that need to be addressed. To ensure that noise does not alias, the bandwidth of the ADC input signal must be limited. This is not a small problem.

Typically, amplifier selection is based on the specification of the product of large signal bandwidth (ie slew rate) and gain bandwidth to cover the worst-case scenario of our input signal, which defines the faster events our ADC can track.

However, the effective noise bandwidth of the amplifier is equivalent to the small-signal bandwidth (typically considering signals less than 10 mV pp), which is usually at least four to five times higher than the large-signal bandwidth.

In other words, if our large-signal specification was chosen to be 500 kHz, the small-signal bandwidth could easily be 2 MHz or 3 MHz, potentially allowing the ADC to sample a lot of noise. Therefore, the small signal bandwidth should be limited externally before feeding the analog signal into the ADC, otherwise the measured noise will be three to four times the ADC datasheet specification, which is not good.

Maximize the performance of your Sigma-Delta ADC driver
Figure 3. Noninverting amplifier configuration.

Amplifier Noise Referenced to Output RTO

T is the temperature in Kelvin, keeping in mind that the thermal noise generated by the amplifier depends on the amplifier gain and total system bandwidth. An example circuit is shown in Figure 3, and the noise sources are summarized as follows:

k is the Boltzmann constant (1.38 × 10−23 J/K), the resistance value is expressed in Ω, and BW refers to the small-signal bandwidth.

The preceding equations clearly demonstrate the importance of adding a low-pass filter with sufficient attenuation before the ADC input pins to minimize sampling noise, since noise is proportional to the square root of the bandwidth. Typically, a first-order low-pass filter implemented using discrete resistors and capacitors has a cutoff frequency low enough to remove most of the broadband noise. The added benefit of a first-order low-pass filter is to reduce the amplitude of any other larger signals outside the band of interest before they are sampled by the ADC and may alias.

However, that’s not all. The internal ADC switch resistors and capacitors define the analog input bandwidth, but also create a time-domain charge-discharge cycle due to changes in the input signal. Each time the switch (external circuit connected to the sampling ADC capacitor) is closed, the internal capacitor voltage may differ from the voltage previously stored on the sampling capacitor.

What is the rebate issue?

Classic analog question: “If you have two capacitors in parallel with a switch, the switch is open, and one capacitor stores some energy, what happens to both capacitors when the switch is closed?”

The answer depends on the ratio between the energy stored in the charging capacitor and the capacitor. For example, if two capacitors are of the same value, energy will be shared between them and the voltage measured across the capacitor terminals will be halved, as shown in Figure 4.

Maximize the performance of your Sigma-Delta ADC driver
Figure 4. Charged (left) and uncharged (right) capacitors.

That’s the kickback issue.

Some ADCs perform an internal calibration to compensate for internal errors, called auto-zero calibration. These procedures bring the sampling capacitor to a voltage close to the power rail or another voltage, such as the reference voltage divided by 2.

This means that the external signal (which must hold the analog value in order to get a new sample) buffered by the amplifier and sampling capacitor is usually not at the same potential (voltage). Therefore, the sampling capacitor must be charged or discharged to bring it to the same potential as the buffer output. The energy required for this process will come from external capacitors (capacitors from the low pass RC filter) and external buffers. This redistribution of charge and stabilization of the voltage takes a finite period of time during which the voltage at various points in the circuit is disturbed, as shown in Figure 1. There is usually a lot of charge redistributed, which is the equivalent of current flowing into or out of the amplifier and into the capacitor.

The result is that the amplifier should be able to charge/discharge the external capacitor of the low pass filter and the sampling capacitor of the ADC in a very limited time, while the current limiter is added by the low pass filter resistor.

More specifically, the amplifier should be able to charge/discharge the capacitor from the sampling capacitor and an external source within a given error range. The cutoff frequency of the external low-pass filter should be slightly higher than the band of interest, which is defined by the filter’s time constant, the number of bits of the ADC, and the worst-case conversion between samples — that is, we should be able to accurately Worst input step size measured.

How do we address rebates?

An easier way to solve this problem is to choose an amplifier with sufficient slew rate, bandwidth gain product, open loop gain, and CMRR, and place the highest capacitance you can possibly find on the market at the output, with a resistance small enough for the low pass filter bandwidth requirements.

Since the capacitor is really big, the kickback problem is negligible and the bandwidth is limited by the LP filter, so the problem is solved, right?

bad news. The previous solution won’t work, but if you’re curious and try the previous setup, you’ll find two things: the capacitor will be the size of a condensed milk container, and the amplifier won’t be like it’s connected to the output.

The performance of an amplifier depends on the imaginary load seen by the amplifier. In this case, the penalty for the low-pass filter is the degradation of THD and settling time. The increase in settling time prevents the amplifier from charging the capacitors, making the voltage sampled by the ADC the correct final voltage. This will cause further nonlinearity in the ADC output.

To illustrate the previous statement, Figure 5 shows the difference in performance between different amplifier output currents or resistive loads. Figure 6 shows the small signal overshoot caused by capacitive loading, which affects settling time and linearity.

Maximize the performance of your Sigma-Delta ADC driver
Figure 6. Small-signal transfer response versus load for the ADA4896-2.

To minimize this problem, the amplifier output should be isolated from the external capacitor by the series resistor of the low-pass filter.

The resistors should be high enough to ensure that the buffer does not see an imaginary impedance, but small enough to meet the required input system bandwidth and to minimize the resistance on the resistor due to current flowing from the buffer. IR drop, which can cause a voltage drop where the amplifier may not settle fast enough. At the same time, the resistor should allow the external capacitor to be reduced to a value small enough to minimize kickback without affecting stability.

You can find more information here.

Fortunately, there are tools that allow us to predict the combined performance of DACs, amplifiers, and filters, such as precision ADC driver tools.

The tool can simulate kickback as well as noise and distortion performance, as shown in Figure 7.

Maximize the performance of your Sigma-Delta ADC driver
Figure 7. Precision ADC driver tool simulation.

Rules of Thumb for Low Pass Filters

Typically, you see first-order low-pass filters in many proposals, but why isn’t anyone using higher-order filters? Unless your equipment will be used in an application with specific requirements to remove large out-of-band interference or harmonics from the input signal, increasing the filter order will add an extra layer of complexity to your system. In general, the trade-off is to make the small signal bandwidth slightly higher than you need, which will affect the noise, but at the cost of being able to drive the ADC input stage easily, and reducing power and cost because of the amplifier.

Reduce the burden on

We mentioned earlier that amplifiers don’t like imaginary impedances and/or supply high currents, an element added by capacitors to minimize kickback issues.

The only way to improve the situation is to reduce the rebate itself. This solution has been adopted by the latest ADI converters such as the AD7768 and AD4000.

Each device uses a different solution due to the different converter architectures. The AD4000 SAR ADC can operate from supplies below the analog input range. The solution used is called Hi-Z mode, which is only available for sampling frequencies below 100 kHz.

In the AD7768, the power supply is at or above the analog input range. The solution employed by the AD7768 is called a precharge buffer, which operates at the highest ADC sampling frequency, as opposed to high-impedance mode.

Both solutions are based on the same operating principle; the main difficulty in driving an ADC is capacitive charge redistribution. In other words, when the internal switch reconnects the sampling capacitor, the lower the voltage drop seen by the input buffer and the low-pass filter, the lower the voltage jump, thus minimizing the ADC input current. Therefore, the easier it is to drive the ADC, the more the settling time is reduced. The voltage drop across the filter resistors is reduced, resulting in improved AC performance.

The effect of input current on the precharge buffer and high-impedance enable and disable is shown in Figure 8.

Maximize the performance of your Sigma-Delta ADC driver
Figure 8. Input current.

The higher the input current, the higher (ie, faster) the amplifier bandwidth should be. Therefore, the bandwidth of the input low-pass filter should be higher, which also affects the noise.

For example, for a 1 kHz input signal sampled at 1 MSPS, use SINAD to treat harmonics as noise performance. At different filter cutoff frequencies, we get the results shown in Figure 9.

Maximize the performance of your Sigma-Delta ADC driver
Figure 9. AD4003 SINAD versus input BW, with and without high-impedance mode.

The graph above shows that the lower input current (hi-Z mode on) reduces the cut-off filter frequency requirement, as well as the IR drop in the filter resistor value, resulting in improved ADC performance compared to the exact same configuration but with the hi-Z mode off .

In Figure 9, it can be observed that by increasing the input filter cutoff frequency, the external amplifier can charge/discharge the sampling capacitor faster, but at the cost of higher noise. For example, with Hi-Z mode on, the noise sampled at 500 kHz is less than 1.3 MHz. Therefore, SINAD is better at 500 kHZ input bandwidth. In addition, the capacitance required for the low-pass filter is reduced, thereby improving the performance of the amplifier driver.

Circuit Design Advantages

The addition of these easier-to-drive or offload features implemented in ADI’s latest ADCs has had some major impacts on the entire signal chain. A key advantage for ADC designers to introduce some drive issues into the ADC chip itself is that a solution can be designed to meet the signal requirements of that ADC as efficiently as possible, thereby addressing issues including input bandwidth and amplifier stability.

Less current into the ADC input, and therefore less kickback, means the amplifier needs to handle lower voltage steps, but still have the same full sampling period as a standard switched capacitor input.

Having a smaller step voltage to settle (ramp to final value) in a given time period is the same as having a longer time to settle a larger step. The net result is that the amplifier now does not need such a wide bandwidth to sufficiently settle the input to the same final value. Lower bandwidth usually means lower power in the amplifier.

Another way to look at this is to imagine how an amplifier that typically does not have enough bandwidth to stabilize a given ADC input can now achieve sufficient stabilization when the precharge buffer is enabled.

ADI application note AN-1384 demonstrates the achievable performance of a range of amplifiers when used with the AD7768 in each of its three power modes. One of the amplifiers shown in this document, the ADA4500-2, shows that it is difficult to stabilize the input of the AD7768 in medium power mode (THD >-96 dB) when the precharge buffer is not used. However, when the precharge buffer is enabled, performance improves significantly to better than −110 dB THD.

Since the ADA4500-2 is a 10 MHz bandwidth amplifier and the bandwidth required to stabilize the AD7768 in a given mode is about 12 MHz, we see that it is now possible to use this lower bandwidth amplifier with ease of drive. By this In this way, these features not only make the design of the front-end snubber circuit easier, but also allow more freedom in choosing components to stay within system power or thermal limits.

The second advantage of reducing the current flowing into the ADC analog input pins is that less current is now flowing through the series resistor used as part of the input RC network.

For traditional ADC inputs, the relatively large current means that only a small value resistor can be used, otherwise a large voltage drop will occur across the resistor. The larger voltage drop here can cause gain errors or linearity errors in the ADC conversion results.

However, using smaller resistor values ​​has its challenges. Using smaller resistors to achieve the same RC bandwidth means using larger capacitors. However, this combination of large capacitance and small resistance can cause instability in the buffer amplifier.

The reduction in current encountered when using the easy-to-drive feature means that larger value resistors can be used without compromising performance and ensuring system stability.

Circuit performance advantage

Considering the benefits to circuit design that we’ve already said, there are obviously performance benefits, or opportunities to use these features to further improve performance.

The benefits already mentioned are the ability to use lower bandwidth amplifiers to achieve better performance, which can also be used to scale the performance of a more optimized system. For example, even if the input signal settles well, there may still be some mismatch between the inputs as eventual settling occurs. So, for example, enabling the precharge buffer will mean that the final settling is much smaller, so the highest level of THD can be achieved where it was not possible before.

The reduction in current through the series resistors of the RC network also benefits performance. Furthermore, not only is the input current significantly reduced, but it is almost independent of the input voltage. Improved THD can be achieved because any mismatch in the resistors on the input pair results in a smaller voltage difference at the ADC input and the voltage drop is independent of the signal.

Lower input current also affects offset and gain accuracy. Changes in component values ​​per channel or per physical board are less likely to cause large changes in offset and gain errors due to the reduction in absolute current as well as the reduction in signal-dependent current variation (for the same reasons, more A low current results in a smaller voltage across the series resistor). Using precharged buffers allows for better absolute offset and gain error specifications, as well as consistent performance across boards or channels within the system.

Lower current has another benefit in systems where the ADC sampling rate is varied to accommodate different signal acquisition needs, such as in data acquisition cards. Without a precharge buffer, the voltage drop across the input passives would vary with the sampling rate of the ADC because the ADC input capacitors would charge and discharge more frequently at higher sampling rates. This applies to both the analog input path and the reference input path, and this voltage change is seen by the ADC as sampling rate-dependent offset and gain errors.

However, with the precharge buffer enabled, the absolute current and absolute voltage drop start off much smaller, so the change in voltage will be much smaller as the ADC sampling rate changes. In the end system, this means that as the sampling rate is adjusted, the need to recalibrate the system offset and gain errors decreases, and the offset and gain errors are less sensitive to changes in the ADC sampling rate.


One of the main benefits of easy-to-use features has to do with total cost of ownership. Different aspects of design and performance advantages lead to potentially lower development and operating costs.

Simpler designs mean less design work and faster time to make the first prototype.
A simpler design means a better chance of first-time success in prototyping.
Easier-to-drive features allow the use of lower bandwidths and therefore lower-cost amplifiers.
The benefits of offset and gain can reduce factory calibration.
Performance improvements can result in fewer on-site or on-demand calibrations, resulting in reduced downtime and/or increased throughput.

Real world example using AD7768-1

Table 2 shows some measurements from the AN-1384 application note to help designers select the appropriate amplifier to drive the AD7768-1 ADC. The examples in the table show that when precharging is enabled on some amplifiers, there can be significant improvements. The reason for the THD improvement in particular is the combined effect of the aforementioned reduced burden imposed by the ADC on the drive circuit. For example, a configuration using the ADA4945-1 amplifier increases THD by 4 dB when the precharge buffer is enabled. Likewise, the ADA4807-2 circuit can achieve an 18 dB increase in THD. These examples show that amplifiers capable of achieving reasonable performance on their own can achieve leading performance levels when combined with the easy-to-drive features found in many of ADI’s latest ADCs.

Table 2. AD7768-1 Performance with Various Amplifiers


Precharge buffer

Signal-to-noise ratio (dB)

Total Harmonic Distortion (dB)

Signal-to-noise ratio (dB)









































Designing a circuit to drive an unbuffered ADC is not an easy task, requiring appropriate approaches and trade-offs due to the converter’s kickback and bandwidth requirements. Many times, the required circuitry will define overall system performance in terms of THD, SNR, and power consumption.

The latest ADI precision converters for SAR and sigma-delta technologies integrate a set of features to minimize converter input current. This minimizes kickback and greatly reduces and simplifies external circuitry, enabling a previously unachievable number of specifications. This makes SAR and sigma-delta techniques easier to use, reduces engineering time, and improves system specifications.

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