Xilinx Preprocessing Solutions for 3G LTE Base Station Designs

1 Introduction

Long Term Evolution (LTE) [1]The cellular standard is one of two components of the 3GPP 3G evolution, the other being the HSPA evolution. As shown in Figure 1.0. The LTE Radio Access Network (RAN) specification is scheduled for completion in early 2008, with the conformance test specification expected to be ready by August 2008.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 1.0 Evolution Route from 3GPP to UMTS
LTE has many goals[2], the focus of LTE is to exceed UMTS and meet the various needs of wireless users throughout the 10-year period. This includes lowering costs for wireless users as well as network operators; on the other hand, providing better variety of services in the form of service differentiation, while providing lower latency and higher data rates.
Various better services provided in the form of service differentiation can be achieved by link adaptation based on the QOS concept. In LTE, link adaptation goes beyond what HSDPA can provide, although HSDPA can provide link adaptation in the time domain in response to changing channel conditions, LTE can also provide frequency adaptation.
In the data rate area, LTE is expected to provide a peak downlink (DL) rate of 100Mbps and a peak uplink (UL) rate of 50Mbps, providing spectral efficiencies of 5 bit/s/Hz and 2.5 bit/s/Hz, respectively. This can be achieved using OFDM and complementary MIMO techniques. Lower latency is achieved through a flat network architecture. The adopted network architecture is based on IP (Internet Protocol) with shorter PHY processing time, as shown in Figure 2.0, in addition to various higher layer functions implemented in the eNodeB (eNB) of LTE. Compared to UMTS, the LTE network architecture reduces the number of nodes along the data path from four to two.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 2.0 Overview of Evolved UTRAN
2. Key elements of LTE
For the uplink, LTE radio access will be based on Single-Carrier Frequency Division Multiple Access (SC-FDMA)[5]. The good peak-to-average power ratio (PAPR) of the SC-FDMA waveform drives the adoption of SC-FDMA in the uplink. With a lower PAPR, the operation of the radio frequency power amplifier (RFPA) can be achieved with higher efficiency, resulting in longer battery life in the mobile phone. For the downlink, the classic OFDMA scheme can be used.
In addition to modulation, another key element is the availability of scheduling-dependent channel conditions. This allows the time-frequency resources in the shared channel to be dynamically shared among users. The scheduling interval – as alluded to – is based on a time division of 1ms and a frequency division of 180KHz. Likewise, the implementation of the scheduler at the MAC layer is a key element in ensuring downlink performance, as it determines the rate employed by each link. Like HSDPA hybrid ARQ that exists at the MAC layer, soft combining is employed in the form of multiple parallel stop-and-wait ARQ processes. The hybrid ARQ scheme is based on incremental redundancy (IR) for retransmission, and in addition to the above key elements, LTE will make multi-antenna support an integral part of the specification. Receive and transmit diversity schemes, beamforming, and spatial multiplexing will all be supported.
One of the goals of an LTE system is that it needs to allow flexible upgrades from 2G/3G to LTE. Because of this, spanning 1.25 MHz to 20
A flexible spectrum allocation of MHz should be available, and the LTE system should be able to operate between 450 MHz and 2.6GHz. In other words, the bandwidth of the LTE specification is Bandwidth agnostic.
Another point worth mentioning is that, unlike UMTS, LTE provides a combination of FDD/TDD and TDD schemes based on a single OFDMA radio access technology. The TDD scheme is called frame structure 2 and supports coexistence with TD-SCDMA.
3. Key elements of the LTE physical layer
LTE provides two types of frame structures on the basis of 10ms radio frame using common radio access technology. The two types of frame structures are FDD/Half-FDD called Type 1 and TDD called Type 2, which are based on 10ms radio frames, each radio frame has 20 time slots, and each time slot occupies 0.5 ms. Type 2 frame structure is provided for coexistence with TD-SCDMA, as shown in Figure 3.0. Note that the TD-SCDMA frame structure has 10 slots in a 5ms subframe. 3 of the 10 slots – DwPTS, GP and UpPTS – are dedicated slots, which are duplicated in LTE frame structure type 2.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 3.0 TDD Type 2 Frame Structure
The core capability of an LTE system that provides link adaptation in the time and frequency domains is the adoption of OFDMA schemes for the downlink. This means that downlink physical resources are defined in terms of one OFDM subcarrier and one OFDM symbol period, which are called resource elements (REs). A total of 84 REs constitute one resource block (RB), which consists of 12 subcarriers over a period of one slot (0.5ms) with 7 OFDM symbols. Because of this, the downlink transmission signal is defined according to the Resource Grid (RG) as depicted in Figure 4.0 such that each user has two REs corresponding to two time slots (1 ms).
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 4.0 Downlink resource grid for LTE
The key physical layer parameters described in Table 1.0 are a function of the allocated frequency bandwidth.
Table 1.0 Key parameters of DL physical layer
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
4. Important Features of LTE Baseband Processing
The downlink physical layer for Tx and Rx is shown in Figure 3.0. Note that it can be decomposed into two types of processing, namely symbol rate processing and sample rate processing. As can be seen from Figure 3.0, the symbol rate handling is simpler compared to the WCDMA-based UMTS standard.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 5.0 3GPP LTE downlink processing
As in UMTS, the challenge for LTE base station design is the processing of the uplink. In the case of LTE, this is further combined with a short processing time requirement to achieve lower latency, while at the Node B having higher layer functions than the RNC.
In this section we review various challenges and solutions from both micro and macro perspectives.
At the micro level, especially for the uplink signal chain as shown in Figure 6.0, the LTE delay budget is mainly defined by the 8ms latency of the HARQ round trip, that is, the time between the initial transmission and the retransmission. Consider twice the transmission time of 1ms, leaving just 6ms for sending and receiving data. That means that the LTE uplink processing must meet the delay budget proposed by the following function within 3 ms. they are, respectively:
• channel estimation delay;
• demodulation;
• Rate matching and IR combination;
• Turbo decoding;
• MAC/RLC processing;
• UL/DL time offset.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 6.0 LTE uplink signal chain
Given the short processing time required, it is therefore crucial that important modules such as iDFT used in SC-FDMA demodulation, as well as turbo decoding, must be completed in the shortest possible time. Xilinx provides IP core solutions that enable base station designers to achieve the goals of iDFT and Turbo Decoding applications.
Taking iDFT processing as shown in Figure 7.0 as an example, after channel estimation, the maximum processing time available for iDFT processing in the worst case is 40us. Xilinx’s iDFT solution enables all multiples of 12 point lengths to have prime factors of 2, 3, and 5 to meet processing time requirements. In addition to FFT/iFFT – both processing are available with DSP or FPGA, there is a clear advantage to doing iDFT in FPGA because the DSP’s bit-reversed addressing is only suitable for radix 2. Similarly, in order to efficiently implement decoding in parallel, Xilinx’s turbo-decoding IP core for LTE with QPP interleaver uses a clock speed of 400MHz for 8 iterations of the maximum code block length shown in Figure 8.0. Takes 40us decoding time.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 7.0 LTE uplink iDFT processing requirements
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs

Figure 8.0 Xilinx Turbo Decoder Performance vs. Module Size and Number of Processing Units

Because of the greater impact on meeting the uplink processing requirements, you must consider the base station design at the macro level, that is, how the baseband design of the base station is divided. Currently, base station vendors can use FPGAs as coprocessors to perform turbo coding to meet throughput requirements. Other related modules as iDFT or RACH pre-detection are shown in Figure 9.0.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 9.0 FPGA as a coprocessor for LTE
However, the challenge here is the delay caused by the interconnection between the FPGA and DSP. We will demonstrate using an uplink example based on a common SRIO interface with the following parameters:
• 10 MHz bandwidth, short CP, single sector;
• no retransmission;
• 4 HARQ processing;
• No spatial multiplexing;
• Based on estimated turbo decode duration;
• SRIO: 3.125 Gb, 1x lane, 8/10 encoding, 25 bits overhead per pickup;
• Transfer time for DDR2 memory, 200 MHz, 32-bit read-only.
Table 2.0 shows an example of the calculations for different services—much better than worst case—including encoding time that must not exceed 1000us total time and delay for sRIO transmission.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Table 2.0 Example of Uplink Processing Time
From the above table we can conclude as follows:
• Significant delays occurred in SRIO transfers;
• Turbocoding needs to be implemented in parallel.
The main problem here is that the latency and data rate requirements especially present challenges for co-processing methods utilizing a single SRIO link, as it incurs up to 400us latency for the 20MHz bandwidth case, which is already 40 times the available processing time %.
To address latency issues, it is better to use FPGA-based preprocessing methods instead of FPGAs as coprocessor methods. This means that the complete PHY layer processing needs to be implemented in the FPGA, while the DSP processor acts as the controller and performs various functions of the higher layers. As shown in Figure 10.0. Using the preprocessing method for the DSP processor, the DSP processor can replace the network processor or reduce the network processor function to only centralized PDCP processing and backhaul interface. Another advantage of taking this approach is that the FPGA can be used for MAC acceleration functions to compensate for the low control code performance present on the DSP. Another approach is to use the FPGA as a preprocessor to the network processor, as shown in Figure 11.0.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 10.0 FPGA Preprocessing Using DSP Architecture
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 11.0 FPGA Preprocessing Using Network Processor Architecture
All in all, these two approaches have several advantages in addition to overcoming the latency issue, such as being prepared for various future changes to the specification.
5. Xilinx LTE Baseband Reference Solution
Xilinx recently demonstrated 3GPP compliant LTE for PDSCH at Mobile World Congress 2008 in Barcelona
Standard LTE baseband downlink solution.
The reference solution consists of a variety of related Xilinx LTE IP cores including turbo encode/decode, rate matching, FFT/iFFT with cyclic prefix insertion, and QAM mapper and demapper. The downstream transmit and receive chain of this reference solution is shown in Figure 5.0.This reference solution is also suitable for various IP cores already developed for LTE[3]Provides system-level verification.
At bandwidths above 10 MHz, Xilinx successfully demonstrated video streams well above 100Mbps. The video streaming-oriented reference application used in this successful demonstration is based on an open source VideoLan Server running on a mainframe PC. The LTE baseband reference solution is located on two recently released ML507 boards. Each board communicates with the host PC via a Gigabit Ethernet link. The UDP packets sent by the host PC are first processed by the tri-state Ethernet MAC module (TEMAC) and then through the Lightweight IP stack (LWIP) before entering the transmit (TX) module of the LTE base station reference solution. The I/Q data from the TX module is output to another ML507 board with the LTE receive (RX) function chain through the Aurora link for processing.
Figure 12.0 shows the setup at MWC 2008, while Figure 13.0 depicts the various modules of the Xilinx LTE Baseband Reference Design Demonstration Platform.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 12.0 Xilinx LTE Baseband Reference Design Demonstration
With the release of the LTE baseband reference design, Xilinx has once again demonstrated its leadership in wireless solutions and is further committed to supporting This is particularly important as the LTE standard continues to evolve) LTE solutions.
Xilinx Preprocessing Solutions for 3G LTE Base Station Designs
Figure 13.0 Xilinx LTE Baseband Reference Design System Block Diagram
[1] 3GPP TS 36.104 V8.0.0 (2007-12), E-UTRA Basestation Radio Transmission
and Reception
[2] “Technical Solutions for the 3G Long-Term Evolutions”, Hannes Ekstrom
et al., IEEE Communication Magazine, March 2006
[3] “Implementing the Next Generation of Wireless Standards using Virtex-5
FXT”, Rob Payne, Xilinx Xcell magazine, 2008
[4] “3G Evolution, HSPA and LTE for Mobile Broadband”, Erik Dahlman et al
al., ELSEVIER, 2007
[5] “Single Carrier FDMA for Uplink Wireless Transmission”, Hyung G. Myung
et. Al., IEEE Vehicular Technology, Magazine, September 2006, page 30
About the authors: Dr. Wen Demin, senior member of IEEE, system architect of wireless infrastructure vertical market at Xilinx; Jorg Kohlschmidt, system architect of wireless infrastructure vertical market at Xilinx.

The Links:   AA121XH03 IP-260-CV